This application claims the priority of Korean Patent Application No. 04-47638, filed on Jun. 24, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field
This invention relates to a coding system and method and, more particularly, to a voltage level coding system and method.
2. Background
FIG. 1 is a block diagram of a typical data transmission system 100, including a transmitter 102 and receiver 104. The transmitter 102 receives a digital signal DATA_IN and converts it into a transmissible analog DATA signal using its Digital-To-Analog converter (DAC) 106. The transmitter 102 transmits the analog signal DATA to an Analog-To-Digital converter (ADC) 108 in the receiver 104. The ADC 108 converts the analog signal DATA into the digital signal DATA_OUT.
The transmitter 102 and, more particularly, the ADC 106, may encode the DATA_IN signal before transmitting it as the DATA signal to the receiver 104. The transmitter 102 may encode the DATA_IN signal using a variety of transmission codes including 8B/10B coding.
8B/10B coding is well suited for and widely used in high speed local area networks and computer links because it is a Direct Current (DC) balanced code. A DC balanced transmission code—a code that is DC free or has a constant DC level regardless of data patterns—is highly desirable because it allows transmission system simplification. This simplification ultimately reduces system costs and may improve reliability.
8B/10B coding involves examining each data octet and assigning a 10 bit code. One approach involves splitting 8 bit wide data into two packets or nibbles. The first nibble includes the 5 least significant bits while the second nibble includes the 3 most significant bits. The 5 bit nibbles are encoded into a 6 bit code and the 3 bit nibbles are encoded into 4 bit code. Both encoded nibbles form the 10 bit code packet that is serially transmitted from, e.g., the transmitter 102 to the receiver 104. 8B/10B coding tables are well known and shown in, for example, U.S. Pat. No. 5,387,911 to Gleichert, issued Feb. 7, 1995.
The 10 bit code packets must either contain five ones and five zeros or four ones and six zeros, or six ones and four zeros. This ensures that too many consecutive ones and zeros do not occur between code packets. To maintain the DC balance, a calculation called running disparity is used to keep the number of zeros transmitted the same as the number of transmitted ones.
8B/10B coding is disadvantageous for several reasons. One disadvantage is that 8B/10B coding uses 10 bits for each 8 bits of data and therefore drops data rate speed relative to line speed. For instance, to gain a data rate of 1 Gbps, the line speed has to be 10/8×1=1.25 Gbps.
Another disadvantage is that transitions between the highest and lowest levels decrease data transmission frequency characteristics. FIG. 2 is a diagram of voltage amplitude over time for 8B/10B coded data with a variety of transitions between different levels superimposed over one another. FIG. 3 is an 8B/10B coding state transition diagram. FIGS. 2 and 3 assume a 1.2V voltage level produces a logic state 00 and a 1.8V voltage level produces a logic state 10. Referring to FIGS. 2 and 3, the diagrams show the response of various 8B/10B coded packets as they transition from one state to another, e.g., from a 10 to 11 to 10 or from 11 to 00 to 11, and so on. As shown in FIG. 3, the longest transition occurs when the coded packets transition between states 00 and 10 or vice versa. These long state transitions create a wide eye opening that adversely affects high frequency data transmission because the larger the voltage transition, the longer it takes the signal to reach the appropriate voltage signal level and consequently, the appropriate code state.
Accordingly, a need remains for an improved coding system and method.